1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a non-volatile memory cell and manufacturing method thereof.
2. Description of the Related Art
Among various types of non-volatile memory products, electrically erasable programmable read-only memory (EEPROM) is a memory device that allows multiple data writing, reading and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, it has been broadly applied in personal computer and other electronic equipment. A typical EEPROM has a polysilicon floating gate and a polysilicon control gate. To program data into the memory device, electrons are injected into the floating gate. The injected electrons will distribute evenly across the entire polysilicon floating gate. However, a defective tunneling oxide layer underneath the polysilicon floating gate defective would result in leakage current adversely affecting the reliability of the device.
To avoid leakage current in the EEPROM device, a charge-trapping layer is used instead of the conventional polysilicon floating gate. The charge-trapping layer is fabricated using silicon nitride, for example. In general, the silicon nitride charge-trapping layer is sandwiched between a pair of silicon oxide layers to form an oxide-nitride-oxide composite stack structure. The EEPROM device with the stacked gate structure is known as a silicon/oxide/nitride/oxide/silicon (SONOS) memory device.
FIG. 1 is a schematic cross-sectional view of a conventional SONOS memory cell. As shown in FIG. 1, the SONOS memory cell includes a substrate 100, a composite dielectric layer 102 having a silicon oxide layer 102a, a silicon nitride layer 102b and a silicon oxide layer 102c, a control gate 104, a drain region 106a and a source region 106b. The silicon oxide layer 102a/silicon nitride layer 102b/silicon oxide layer 102c composite dielectric layer 102 and the control gate 104 are sequentially disposed over the substrate 100 to form a stacked gate structure 108. A channel region 110 is formed in the substrate 100 underneath the stacked gate structure 108. The drain region 106a and the source region 106b are disposed in the substrate 100 next to each side of the stacked gate structure 108.
With the miniaturization of integrated circuit devices, length of the control gate in each SONOS memory cell is reduced. However, a reduction of gate length will shorten the channel 110 underneath the silicon oxide layer 102a. Hence, when data is programmed into the memory cell, the probability of a punch through between the drain region and the source region is increased thereby affecting its electrical performance. Furthermore, width 104a of the channel 110 has significant effect on the storage efficiency of the SONOS memory cell. In general, the storage efficiency will deteriorate with a shortening of the gate width 104a. In addition, a reduction of memory cell dimensions will eventually encounter critical dimension problem in photolithographic process. Thus, any method capable of increasing the coupling rate of a miniaturized SONOS memory cells is eagerly sought.
On the other hand, with the invention of more powerful computer software, the demand for a larger memory capacity by the software program also increases considerably. The present device miniaturization trend and memory multiplication demands substantial modifications of the SONOS memory cell structure and manufacturing method thereof. In the deep sub-micron fabrication regime, how to increase memory storage capacity within a smaller space is now a common research topic.